1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly, to improvements of an electrostatic capacity device in a semiconductor memory device. More specifically, the present invention relates to a structure for providing a fast sensing operation in which a read-out potential appearing on a bit line in selecting a word line is detected and amplified, with the use of the improved electrostatic capacity device.
2. Description of the Background Art
FIG. 1 is a diagram exemplifying a schematic structure of an entire read-out portion in a conventional dynamic random access memory. Referring to FIG. 1, the dynamic random access memory comprises a memory cell array MA constituted of memory cells arranged in a matrix of rows and columns and each storing information, an address buffer AB responsive to an externally applied external address for generating an internal address, an X decoder ADX for decoding an internal row address received from the address buffer AB for selecting a corresponding row in the memory cell array MA, and a Y decoder ADY for decoding an internal column address received from the address buffer AB for selecting a column corresponding thereto in the memory cell array MA.
The address buffer AB receives a row address specifying a row in the memory, cell array MA and a column address specifying a column in the memory cell array MA in a time division multiplexing manner and generates the internal row address and the internal column address at predetermined timings to apply them to the X decoder ADX and to the Y decoder ADY, respectively.
To read out data in a memory cell specified by the external address, the dynamic random access memory further comprises a sense amplifier for detecting and amplifying data in the memory cells connected to a row selected by a decoded row address signal from the X decoder ADX, an input/output interface (I/O) responsive to a decoded column address signal from the Y decoder ADY for transmitting data of a selected memory cell among the memory cells connected to the selected single row, and connected to the corresponding column, to an output buffer OB, and the output buffer OB for transmitting the memory cell data received through the input/output interface (I/O), to a device external to the dynamic random access memory. In FIG. 1, there are shown the sense amplifier and the input/output interface (I/O) as constituting a single block SI. The output buffer OB receives the read-out data transmitted from the block SI and converts the same into corresponding output data Dout for output.
Peripheral circuitry CG for generation of control signals is provided to generate the control signals for controlling various operating timings of the dynamic random access memory. The peripheral circuitry CG for generation of control signals generates a precharge potential V.sub.B, a word line drive signal Rn, an equalize signal .phi..sub.E, a precharge signal .phi..sub.P, a sense amplifier activating signal .phi..sub.S and the like, as will be described later in detail.
A schematic structure of the memory cell array shown in FIG. 1 and other circuit associated therewith is shown in FIG. 2. Referring to FIG. 2, the memory cell array MA comprises word lines WL1, WL2, . . . and WLn each defining a single row of the memory cell array MA, and bit line pairs BL0 and BL0, BL1 and BL1, . . . and BLm and BLm each having connected memory cells for a single column of the memory cell array MA.
The bit line BL0 and BL0, . . . BLm and BLm each constitute a folded bit line, every two bit lines of which constitute a single bit line pair. More specifically, the bit lines BL0 and BL0 constitute one bit line pair, the bit lines BL1 and BL1 constitute another bit line pair and so forth, until the bit lines BLm and BLm constitute a bit line pair.
Memory cells 1 for storing information are provided at intersections of each of the bit lines BL0, . . . BLm and BLm, and alternate word lines. Therefore, for respective bit line pairs, the memory cell 1 is provided at an intersection of a single word line and either bit line of a single bit line pair. The respective bit line pairs BL0 and BL0, . . . BLm and BLm are provided with a precharge/equalize circuit 150 for equalizing and precharging potentials on the respective bit lines to a predetermined potential V.sub.B while the dynamic random access memory is in its stand-by state.
The respective bit line pairs BL0 and BL0, . . . , BLm and BLm are further provided with a sense amplifier 50 for sensing and amplifying data of the selected memory cell. The sense amplifier 50 is responsive to a first sense amplifier drive signal .phi..sub.A and a second sense amplifier drive signal .phi..sub.B transmitted through a first signal line 14 and a second signal line 17, respectively, for being activated to detect and differentially amplify potential difference on the corresponding bit line pair.
In order to transmit the data of the selected memory cell to the output buffer OB as shown in FIG. 1, the bit line pairs BL0 and BL0, . . . , BLm and BLm are further provided with transfer gates T0 and T0', T1 and T1', . . . and Tm and Tm', respectively, which are responsive to the decoded column address signal from the Y decoder ADY for turning on to connect the corresponding bit line pair with data input/output buses I/O and I/ . The transfer gates T0 and T0, are provided for the bit lines BL0 and BL0, the transfer gates T1 and T1' for the bit lines BL1 and BL1, and the transfer gates Tm and Tm' for the bit line pairs BLm and BLm. A single transfer gate pair turns on in response to the decoded column address signal from the Y decoder ADY thereby connecting the corresponding bit line pair to the input/output buses I/O and I/ .
FIG. 3 is a diagram showing a circuit structure associated with a single bit line pair out of the structure shown in FIG. 2. In particular,.the diagram shows a specific structure of an apparatus for driving the sense amplifier 50.
Referring to FIG. 3, the memory cell 1 comprises a memory capacitor 6 for storing information in the form of charge, and a selection transistor 5 which is responsive to the word line drive signal Rn transmitted onto a word line 3 for turning on to connect the memory capacitor 6 to a bit line 2. The selection transistor 5 comprises an n-channel insulating gate field effect transistor (referred to simply as n-FET hereinafter) having the gate connected to the word line 3 and the source connected to the bit line 2. One electrode of the memory capacitor 6 is connected to the drain of &he selection transistor 5 through a storage node 4 while the other electrode is connected to ground potential GND (practically to a supply potential Vcc).
The precharge/equalize circuit 150 comprises n-FETs 9, 10 and 12. The n-FET 9 is responsive to the precharge signal .phi..sub.P transmitted through a precharge signal transmitting line 11, for turning on to transmit the precharge voltage V.sub.B transmitted through a precharge potential transmitting signal line 8 onto the bit line 2. The n-FET 10 is responsive to the precharge signal .phi..sub.P transmitted through the signal line 11, for turning on to transmit the precharge voltage V.sub.B transmitted through the signal line 8 to another bit line 7. The n-FET 12 is responsive to the equalize signal .phi..sub.E transmitted through an equalize signal transmitting signal line 13, for turning on to electrically short-circuit the bit lines 2 and 7 thereby equalizing the potentials on the bit lines 2 and 7.
The sense amplifier 50 comprises p-channel insulating gate field effect transistors (referred to simply as p-FETs hereinafter) 15 and 16, and n-FETs 18 and 19. The sense amplifier 50 comprises a flip-flop of a CMOS (Complimentary Metal Oxide Semiconductor) structure where one electrode of each of the p-FETs 15 and 16 is cross-coupled with the gate electrode of the other, and also one electrode of each of the n-FETs 18 and 10 is cross-coupled with the gate electrode of the other. A connection node between one electrode of the p-FET 15 and one electrode of the n-FET 18 is connected to the bit line 2 while another connection node between one electrode of the p-FET16 and one electrode of the n-FET 19 is connected to the bit line 7. The other electrodes of the p-FETs 15 and 16 are connected together to a signal line 14 which transmits the first sense amplifier drive signal .phi..sub.A. The other electrodes of the n-FETs 18 and 19 are connected together to a signal line 17 which transmits the second sense amplifier drive signal .phi..sub.B.
Between the signal lines 14 and 17 there are provided n-FETs 26, 27 and 28 for precharging and equalizing potentials on the signal lines 14 and 17 to the predetermined potential V.sub.B. The n-FET26 is responsive to the precharge signal .phi..sub.P transmitted through the signal line 11 for turning on to transmit the predetermined constant precharge voltage V.sub.B transmitted through the signal line 8 onto the signal line 14. The n-FET 27 is responsive to the precharge signal .phi..sub.P transmitted through the signal line 11 for turning on to transmit the precharge potential V.sub.B transmitted through the signal line 8 onto the signal line 17. The n-FET 28 is responsive to the precharge signal .phi..sub.P transmitted through the signal line 11 for turning on to electrically short-circuit the signal lines 14 and 17 thereby equalizing the potentials on the signal lines 14 and 17.
In order to drive the sense amplifier 50, between the signal line 14 and a first source potential supply terminal 24 there is provided a p-FET 22 which is responsive to the first sense amplifier activating signal .phi..sub.S for turning on to connect the signal line 14 to a first power line 31.
Similarly, between the signal line 17 and a second source potential supply terminal 29 there is provided an n-FET 25 which is responsive to the second sense amplifier activating signal .phi..sub.S for turning on to connect the signal line 17 to a second power line 30. The sense amplifier activating signals .phi..sub.S and .phi..sub.S are applied to the gates of the p-FET 22 and the n-FET 25 through signal input terminals 23 and 26, respectively. The supply terminals 24 and 29 are made of bonding pads which have been formed in a peripheral area of a semiconductor chip having the dynamic random access memory formed therein, so as to receive a predetermined potential from an external to the dynamic random access memory.
The bit line 2 has a parasitic capacitance 20 and the bit line 7 has a parasitic capacitance 21. In addition, the second power line 30 has a parasitic resistance 32.
Meanwhile, for simplicity of the drawing, in FIG. 3 there are typically shown only one word line 3 and the memory cell 1 disposed at the intersection between the word line 3 and the bit line 2. In practice, however, a plurality of memory cells are connected to each of the bit lines 2 and 7.
Furthermore, the precharge voltage V.sub.B for precharging the bit lines 2 and 7 and the signal lines 14 and 17 to a predetermined potential is generally set to about a half of the operational supply potential Vcc.
FIG. 4 is a signal waveform diagram showing operation of the circuit structure shown in FIG. 3. In FIG. 4, an operation is shown where information of logic "1" which has bee stored in the memory cell 1 shown in FIG. 3 is read out. In the following, the reading-out operation for the memory cell data will be described with reference to FIGS. 3 and 4.
In a stand-by state between the time t0 and the time t1, the precharge signal .phi..sub.P and the equalize signal .phi..sub.E are both at the "H" level. Therefore, all of the n-FETs 9, 10 and 12, and the n-FETs 26, 27 and 28 are in their on-state to hold the bit lines 2 and 7 and the signal lines 14 and 17 at the predetermined precharge potential V.sub.B (=Vcc/2).
At the beginning of a memory cycle or at the time t1 whereat the stand-by state terminates, the precharge signal .phi..sub.P and the equalize signal .phi..sub.E begin to fall to the "L" level. This causes the n-FETs 9, 10, 12, 26, 27 and 28 to be turned off.
At the time t2, the precharge signal .phi..sub.P and the equalize signal .phi..sub.E reach the "L" level, turning off all of the n-FETs 9, 10, 12, 26, 27 and 28, and then the internal row address is applied from the address buffer AB to the X decoder ADX as shown in FIG. 1, to select a row in the memory cell array MA.
At the time t3, the word line drive signal Rn is transmitted onto a selected word line 3 (assuming that the word line 3 shown in FIG. 3 is selected) to raise potential on the word line 3. This causes the selection transistor 5 in the memory cell 1 to be turned on so that the capacitor 6 in the memory cell 1 is connected to the bit line 2. As a result, charges having been stored at the storage node 4 move to the bit line 2, increasing potential on the bit line 2 by only .DELTA.V. The value V of this potential increase on the bit line 2 is determined depending on capacitance value C6 of the memory capacitor 6, capacitance value C20 of the parasitic capacitance 20 of the bit line 2 and the stored voltage V4 at the storage node 4, which generally amounts to 100 to 200 mV.
At the time t4, the sense amplifier activating signal .phi..sub.S begins to rise while the sense amplifier activating signal .phi..sub.S begins to fall, so that the n-FET 25 and the p-FET 22 are turned on. As a result, the first and second signal lines 14 and 17 are connected to the first and second power lines 31 and 30, respectively, causing the potential on the first signal line 14 to rise and the potential on the second signal line 17 to fall.
The rise and fall of potential on these first and second signal lines 14 and 17 activates the flip-flop circuit (sense amplifier 50) comprising the p-FETs 15 and 16 and the n-FETs 18 and 19, allowing the sensing operation for memory cell data to begin, followed by differential amplification of the minute potential difference .DELTA.V between the bit lines 2 and 7. Meanwhile, since to the bit line 7 is connected no selected memory cell, potential on the bit line 7 remains held at the precharge level of Vcc/2 until the time t4.
In this sensing operation, when the n-FET 19 is turned on as a result of the potential increase on the bit line 2 only by .DELTA.V, with the potential on the second signal line 17 decreased, the charges having been stored in the parasitic capacitance 21 are discharged through the n-FET 19 to the signal line 17, so that potential on the bit line 7 substantially reaches 0 V at the time t5.
On the other hand, the potential decrease on the bit line 7 causes the p-FET 15 to be turned on, through which potential on the first signal line 14 is transmitted to the bit line 2 so that potential on the bit line 2 increases to the Vcc level. The potential on the bit line 2 is transmitted to the storage node 4 through the selection transistor 5 so that potential level at the storage node 4 becomes Vcc-V.sub.TH, allowing restoring of data in the memory cell 1. V.sub.TH represents here threshold voltage of the selection transistor.
When the amplifying operation of the signal potentials on the bit lines 2 and 7 is accomplished by establishing the respective potentials at the supply potential Vcc level and at the ground potential GND level, one column of the memory cell array is selected according to the decoded address signal from the column decoder ADY (see FIG. 1) and the bit lines 2 and 7 are connected to the data input/output buses I/O and I/ (see FIG. 2) until the time t8, whereby the information of the memory cell 1 is read out.
The aforementioned is a description for the operations of reading-out, amplifying and restoring data in a memory cell. When a series of these operations is accomplished, the circuit enters in its stand-by state for the subsequent memory cycle. More specifically, the word line drive signal Rn begins to fall at the time t8 and reaches the ground potential level of "L" at the time t9, and then the selection transistor 5 is turned off, electrically disconnecting the memory cell 1 from the bit line 2 to put the circuit in the stand-by state.
At the time t10, the sense amplifier activating signals .phi..sub.S and .phi..sub.S begin to fall and rise, and at the time t1l reach the low level of ground potential GND and the high level of supply voltage Vcc, respectively, turning off the p-FET 22 and the n-FET 25 so that the sense amplifier 50 is inactivated.
At the time t12, the equalize signal .phi..sub.E begins to rise, turning on the n-FET 12 so that the bit lines 2 and 7 are electrically connected to each other. As a result, charges move from the bit line 2 at a higher potential level to the bit line 7 at a lower potential level and the potentials on the bit lines 2 and 7 together reach the precharge potential V.sub.B (=Vcc/2) approximately at the time t13. At the same time, transfer of charges occurs between the first and second signal lines 14 and 17 which have been put in the high-impedance state due to the p-FET 22 and n-FET 25 in the off-state, and the bit lines 2 and 7, resulting in potential levels of the signal lines 14 and 17 at Vcc/2+.vertline.V.sub.TP .vertline. and Vcc/2-V.sub.TN, respectively. V.sub.TP represents here threshold voltage of the p-FETs 22 and 16 while V.sub.TN represents threshold voltage of the n-FETs 18 and 19.
When the precharge signal .phi..sub.P begins to rise at the time t14, the n-FETs 9, 10, 26, 27 and 28 begin to become conductive. When the precharge signal .phi..sub.P attains the supply voltage Vcc of "H" level at the time t15, all of the n-FETs 9, 10, 22, 26, 27 and 28 are turned on so that the precharge voltage V.sub.B is transmitted to the bit lines 2 and 7 and the signal lines 14 and 17 are electrically connected through the n-FET 28, whereby the two sets of potentials are equalized, respectively. Furthermore, the predetermined precharge voltage V.sub.B is transmitted to the signal lines 14 and 17 through the n-FETs 26 and 27 so that the potentials on the first and second signal lines 14 and 17 become Vcc/2. This transit of the precharge signal .phi..sub.P to the "H" level stabilizes potentials on the bit lines 2 and 7 and the signal lines 14 and 17 in preparation for the subsequent reading-out operation.
As described above, in the reading-out operation of memory cell data in the dynamic random access memory, one bit line of one bit line pair is charged from the Vcc/2+.DELTA.V level to the Vcc level while the other bit line is discharged from the Vcc/2 level to the ground potential of 0 V level (only where logic "1" has been stored in the memory cell). In a case wherein logic "0" has been stored in the selected memory cell, potential of one bit line is discharged from the Vcc/2-.DELTA.V level to the ground potential of 0 V level while the other bit line is charged from the Vcc/2 level to the supply potential of Vcc level.
In other words, in the operation of the sense amplifier, one bit line at a higher potential is charged to the supply voltage Vcc level while the other bit line at a lower potential is discharged to the ground potential level with respect to one bit line pair. This charge and discharge is attained by charging and discharging the capacitors of the bit lines, which is performed between the supply potential terminal 24 and the ground terminal (second supply potential terminal) 29 through the sense amplifier, the first and second signal lines 14 and 17 and the first and second power lines 30 and 31. However, the first and second power lines 31 and 30 are provided with the parasitic resistances 33 and 32 as described above (in the following description, the first power line 31 is referred to simply as power line and the second power line 30 as ground line for convenience of description). The parasitic resistances of the power line 31 and the ground line 30 will be described with reference to FIG. 5.
In FIG. 5, there is shown a schematic layout of a memory cell array, a sense amplifier, a power line 31 and a ground line 30 of a 4 M (mega) bit dynamic random access memory formed on a semiconductor chip 100.
In FIG. 5, the memory cell array MA is divided into 8 sub array blocks MA1 to MA8. Each of the sub arrays MA1 to MA8 has 512K bits, or memory cells arranged in 512 rows and 1024 columns (1K columns). The division of the memory cell array into the sub arrays allows bit lines in the respective sub array blocks to be reduced in length, and the read-out voltage .DELTA.V for the memory cell to be increased. The sub array blocks MA1 to MA8 are provided with the sense amplifier blocks SA1 to SA8, respectively. In the respective sense amplifier blocks SA1 to SA8, since a single sense amplifier is provided for each of the columns in the corresponding sub array block, 1024 sense amplifiers are provided in total.
The ground line 31 extends from a bonding pad 24 to be disposed along and commonly for all of the sub array blocks MA1 to MA8 on the semiconductor chip 100. Likewise, the ground line 30 extends from a pad 29 for the ground potential to be disposed along and commonly for the memory cell array blocks MA1 to MA8 on the semiconductor chip 100. The power line 31 and the ground line 30 are disposed not only for the memory cell array blocks MA1 to MA8, but of course for supplying other peripheral circuits with a predetermined potential. For example, in the vicinity of the bonding pads 24 and 29, each of the power line 31 and the ground line 30 branches to be used for other peripheral circuits such as an address decoder, an address buffer or the like. To avoid complexity of description, here is shown only a structure where supply/ground potential is supplied to those circuit blocks which are associated with the memory cell array blocks MA1 to MA8.
A p-FET 221 and an n-FET 251 are provided to drive the sense amplifiers of the sense amplifier block SA1. Likewise, a p-FET 222 and an n-FET 252 are provided to drive the sense amplifier of the sense amplifier block SA2. For the sense amplifier block SA3, a p-FET 223 and an n-FET 253 are provided, for the sense amplifier block SA7 a p-FET 227 and an n-FET 257, and for the sense amplifier block SA8, a p-FET 228 and an n-FET 258 are provided.
The p-FETs 221 to 228 are responsive to the sense amplifier activating signal .phi..sub.S applied from a signal input node 23, for turning on to connect the sense amplifier activating signal lines in the respective blocks to the ground line 31. The respective n-FETs 251 to 258 are responsive to the sense amplifier activating signal .phi..sub.S transmitted through a signal input node 26, for turning on to connect a signal line in the corresponding sense amplifier block to the ground line 30. The power line 31 and the ground line 30 have parasitic resistance as indicated by broken lines in FIG. 5.
As exemplified in FIG. 5, the power line 31 and the ground lines 30 are disposed substantially from one end of the semiconductor chip 100 to the other. Therefore, the parasitic resistance will be relatively great even if aluminum of low resistivity is employed as the interconnection material. In the structure shown in FIG. 5, for example, the largest possible parasitic resistance of the ground line 30 can be seen with respect to the sense amplifier block SA1 which has been provided furthest away from the pad 29. It is here attempted to calculate the parasitic resistance value of the ground line 30 with respect to this sense amplifier block SA1 in a general 4 M dynamic random access memory as an example. Now, assume that:
aluminum resistance value: 50 m.OMEGA./.quadrature., PA1 aluminum interconnection width: 25 .mu.m, PA1 aluminum interconnection length: 15 mm.
With the values above, the parasitic ground line 30 with respect to the sense amplifier block SA1 is given by the following expression. ##EQU1##
Meanwhile, there are provided memory cells of 1024 columns in the memory cell array MA1, where a single column corresponds to a single bit line pair. This means that there are 1024 discharging bit lines in the sensing operation. Now, assuming that the capacitance per single bit line is about 0.3 pF, the total capacitance of the bit lines participating in the discharging is given by the following expression. ##EQU2## The charges stored in this capacitance C are to be discharged to the ground terminal pad 29 through the n-FET 251 and the parasitic resistance of the ground line 30 in the sensing operation. Then, the time required for this discharging will be calculated. In order to simplify this calculation, it is assumed that size of the n-FET 250 is enlarged enough to have an equivalent resistance which is well smaller than the parasitic resistance of the ground line 30, and the discharge time t is regarded as time constant .tau. of this CR discharge circuit. The discharge time t is given by the following expression. ##EQU3##
The total delay time acceptable in a single memory cycle of the dynamic random access memory is 60 to 80 ns and more than 10% thereof is taken by the discharge time, which amounts to a relatively high proportion.
Furthermore, the above dynamic random access memory is constituted in such a manner that in one memory operation (one memory cycle), not only a single sub array block but also other sub array, blocks operate (in the 4 M bit dynamic random access memory shown in FIG. 5, two sub array blocks operate simultaneously). Therefore, in the sensing operation these plurality of sub array blocks are simultaneously activated so that the discharge in the sensing operation will cause the potential level on the ground line 30 and thus the discharge level of the bit line to increase, resulting in a longer discharge time than the above-mentioned value.
Furthermore, while in the above, description has been made merely on the delay in the discharge operation of the bit line at a lower potential in the sensing operation, the same argument is true of the charge operation for charging the bit line at a higher potential so that also the charge time becomes longer.
The increased time for charging and discharging the bit lines in the sensing operation also leads to an unnecessarily increased time which will be taken for establishing the potentials of the bit lines to the supply potential V.sub.cc level and the ground potential level, so that a problem arises that the memory cell data cannot be read out at a high speed.
Additionally, in a case where numerous bit lines are charged and discharged in the sensing operation as described above, the charging and the discharging currents in a large-capacity dynamic random access memory amount to, for example, as much as 150 mA to 250 mA, causing fluctuation in the supply potential and the ground potential, which may even result in a malfunction of the circuit operation.
The stabilization of supply voltage by providing a bypass condenser formed of a PN junction between the power line and, the ground line is described in "32K.times.8 bits fast SRAM; 10 ns accomplished with thorough countermeasures against noise" Nikkei Electronics, No. 455, 1988, September 5, pp. 133 to 136.